#NMOSlogic
Live, measured metrics for the hashtag #NMOSlogic from the open social web. Every number carries a named source and the time it was fetched. Nothing is estimated.
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Day-by-day usage
measured · fosstodon.org (Mastodon public tags API) · fetched 2026-07-28 18:55 UTC0 uses by 0 unique accounts across the window. Real per-day counts, not estimates. Newest bar is today so far.
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Live pulse
measured · fosstodon.org (Mastodon tag timeline) · fetched 2026-07-28 18:55 UTCEverything below is measured over the latest 5 public posts (spanning ~6390 hours).
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Avg boosts / post: 0.2
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This was how far I went last time. JK flip flop with data gating ("HOLD") and asynchronous reset ("CLR") inputs in NMOS logic. (But don't use this schematic for real, it's still incorrect.) #NMOSLogic
The original estimation was 15 transistors per JK flip-flop, I found negative logic can reduce 15T to at least 13T, saving a few inverters here and there - useful in discrete transistor logic.... When I was reading and simulating the circui
Back to NMOS logic. It appears that I can force-clear a flip-flop simply by shorting its output to ground. In NMOS, a logical 0 will always safely overpower logical 1. This can save many transistors in my digital machine. #NMOSlogic #retroc
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